TRAVIS_PYTHON_VERSION=3.4 TRAVIS_OS_NAME=linux <<<<<< ENV .deploy_to_sourceforge.py .gitignore .travis.yml 0.7 CODE_OF_CONDUCT.md LICENSE README.md README.rst THANKS.txt _config.yml autocorrectpep8_script.sh docs/1.3 docs/index.html docs/make.bat docs/makefile docs/old_files/High Speed True Random Number Generators in Xilinx FPGAs.pdf docs/old_files/IQmodule.png docs/old_files/RedPitaya_HDL_memory_map_rp095officialdesign.odt docs/old_files/attributes.pdf docs/old_files/benchmarks/asyncio_no_correction.png docs/old_files/benchmarks/images/with_timer/asyncio.png docs/old_files/benchmarks/images/with_timer/asyncio_no_correction.png docs/old_files/benchmarks/images/with_timer/my_sleep.png docs/old_files/benchmarks/images/with_timer/processEvents.png docs/old_files/benchmarks/images/with_timer/qeventloop.png docs/old_files/benchmarks/images/with_timer/time.sleep.png docs/old_files/benchmarks/images/without_timer/asyncio.png docs/old_files/benchmarks/images/without_timer/my_sleep.png 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docs/source/developer_guide/api/lockbox.rst docs/source/developer_guide/api/memory_tree.rst docs/source/developer_guide/api/select_property.rst docs/source/developer_guide/api/spectrum.rst docs/source/developer_guide/codingstyle.rst docs/source/developer_guide/codingworkflow.rst docs/source/developer_guide/dist/autodoc.rst docs/source/developer_guide/dist/executable.rst docs/source/developer_guide/dist/index.rst docs/source/developer_guide/dist/release.rst docs/source/developer_guide/fpga_compilation.rst docs/source/developer_guide/index.rst docs/source/developer_guide/unittests.rst docs/source/gallery/index.rst docs/source/index.rst docs/source/indices_and_tables/index.rst docs/source/indices_and_tables/modules.rst docs/source/indices_and_tables/pyrpl.hardware_modules.iir.rst docs/source/indices_and_tables/pyrpl.hardware_modules.rst docs/source/indices_and_tables/pyrpl.rst docs/source/indices_and_tables/pyrpl.software_modules.lockbox.models.rst docs/source/indices_and_tables/pyrpl.software_modules.lockbox.rst docs/source/indices_and_tables/pyrpl.software_modules.rst docs/source/indices_and_tables/pyrpl.test.rst docs/source/indices_and_tables/pyrpl.test.test_hardware_modules.rst docs/source/indices_and_tables/pyrpl.widgets.module_widgets.rst docs/source/indices_and_tables/pyrpl.widgets.rst docs/source/logo.png docs/source/reference_guide/index.rst docs/source/user_guide/basics/index.rst docs/source/user_guide/image.bmp docs/source/user_guide/index.rst docs/source/user_guide/installation/common_problems.rst docs/source/user_guide/installation/hardware_installation.rst docs/source/user_guide/installation/index.rst docs/source/user_guide/installation/pyrpl_installation.rst docs/source/user_guide/installation/redpitaya_welcome.jpg docs/source/user_guide/installation/user_dir.rst docs/source/user_guide/tutorial/index.rst docs/source/user_guide/tutorial/tutorial.html docs/source/user_guide/tutorial/tutorial.ipynb docs/source/user_guide/tutorial/tutorial.rst environment.yml py3.yml pyrpl.spec pyrpl/__init__.py pyrpl/__main__.py pyrpl/_version.py pyrpl/acquisition_module.py pyrpl/async_utils.py pyrpl/attributes.py pyrpl/config/global_config.yml pyrpl/config/nosetests_source.yml pyrpl/config/nosetests_source_dummy_module.yml pyrpl/config/nosetests_source_lockbox.yml pyrpl/curvedb.py pyrpl/errors.py pyrpl/fpga/Makefile pyrpl/fpga/README.md pyrpl/fpga/ip/system.bd pyrpl/fpga/ip/system_bd.tcl pyrpl/fpga/make.bat pyrpl/fpga/out/clock_util.rpt pyrpl/fpga/out/post_imp_drc.rpt pyrpl/fpga/out/post_place_timing_summary.rpt pyrpl/fpga/out/post_route_power.rpt pyrpl/fpga/out/post_route_timing.rpt pyrpl/fpga/out/post_route_timing_summary.rpt pyrpl/fpga/out/post_route_util.rpt pyrpl/fpga/out/post_synth_power.rpt pyrpl/fpga/out/post_synth_timing_summary.rpt pyrpl/fpga/red_pitaya.bin pyrpl/fpga/red_pitaya_vivado.tcl pyrpl/fpga/red_pitaya_withPRNG.bin pyrpl/fpga/rtl/axi_master.v pyrpl/fpga/rtl/axi_slave.v pyrpl/fpga/rtl/axi_wr_fifo.v pyrpl/fpga/rtl/pwm.sv pyrpl/fpga/rtl/red_pitaya_adv_trigger.v pyrpl/fpga/rtl/red_pitaya_ams.v pyrpl/fpga/rtl/red_pitaya_asg.v pyrpl/fpga/rtl/red_pitaya_asg_ch.v pyrpl/fpga/rtl/red_pitaya_compressor_block.v pyrpl/fpga/rtl/red_pitaya_dfilt1.v pyrpl/fpga/rtl/red_pitaya_dsp.v pyrpl/fpga/rtl/red_pitaya_filter_block.v pyrpl/fpga/rtl/red_pitaya_hk.v pyrpl/fpga/rtl/red_pitaya_iir_block.v pyrpl/fpga/rtl/red_pitaya_iir_block.v.current pyrpl/fpga/rtl/red_pitaya_iq_block.v pyrpl/fpga/rtl/red_pitaya_iq_demodulator_block.v pyrpl/fpga/rtl/red_pitaya_iq_fgen_block.v pyrpl/fpga/rtl/red_pitaya_iq_hpf_block.v pyrpl/fpga/rtl/red_pitaya_iq_lpf_block.v pyrpl/fpga/rtl/red_pitaya_iq_modulator_block.v pyrpl/fpga/rtl/red_pitaya_lpf_block.v pyrpl/fpga/rtl/red_pitaya_normalizer_block.v pyrpl/fpga/rtl/red_pitaya_pfd_block.v pyrpl/fpga/rtl/red_pitaya_pid_block.v pyrpl/fpga/rtl/red_pitaya_pid_block_with_normalizer.v pyrpl/fpga/rtl/red_pitaya_pll.sv pyrpl/fpga/rtl/red_pitaya_prng.v pyrpl/fpga/rtl/red_pitaya_product_sat.v pyrpl/fpga/rtl/red_pitaya_ps.v pyrpl/fpga/rtl/red_pitaya_pwm.sv pyrpl/fpga/rtl/red_pitaya_saturate.v pyrpl/fpga/rtl/red_pitaya_scope.v pyrpl/fpga/rtl/red_pitaya_top.v pyrpl/fpga/rtl/red_pitaya_trigger_block.v pyrpl/fpga/sdc/red_pitaya.xdc pyrpl/fpga/settings.sh pyrpl/hardware_modules/__init__.py pyrpl/hardware_modules/ams.py pyrpl/hardware_modules/asg.py pyrpl/hardware_modules/dsp.py pyrpl/hardware_modules/filter.py pyrpl/hardware_modules/hk.py pyrpl/hardware_modules/iir/__init__.py pyrpl/hardware_modules/iir/iir.py pyrpl/hardware_modules/iir/iir_theory.py pyrpl/hardware_modules/iq.py pyrpl/hardware_modules/pid.py pyrpl/hardware_modules/pwm.py pyrpl/hardware_modules/sampler.py pyrpl/hardware_modules/scope.py pyrpl/hardware_modules/trig.py pyrpl/memory.py pyrpl/module_attributes.py pyrpl/modules.py pyrpl/monitor_server/Makefile pyrpl/monitor_server/monitor_server pyrpl/monitor_server/monitor_server.c pyrpl/monitor_server/monitor_server_0.95 pyrpl/pyrpl.py pyrpl/pyrpl_utils.py pyrpl/redpitaya.py pyrpl/redpitaya_client.py pyrpl/software_modules/__init__.py pyrpl/software_modules/curve_viewer.py pyrpl/software_modules/lockbox/__init__.py pyrpl/software_modules/lockbox/gainoptimizer.py pyrpl/software_modules/lockbox/input.py pyrpl/software_modules/lockbox/lockbox.py pyrpl/software_modules/lockbox/models/__init__.py pyrpl/software_modules/lockbox/models/custom_lockbox_example.py pyrpl/software_modules/lockbox/models/fabryperot.py pyrpl/software_modules/lockbox/models/interferometer.py pyrpl/software_modules/lockbox/models/linear.py pyrpl/software_modules/lockbox/output.py pyrpl/software_modules/lockbox/stage.py pyrpl/software_modules/loop.py pyrpl/software_modules/module_managers.py pyrpl/software_modules/network_analyzer.py pyrpl/software_modules/pyrpl_config.py pyrpl/software_modules/software_pid.py pyrpl/software_modules/spectrum_analyzer.py pyrpl/sshshell.py pyrpl/test/__init__.py pyrpl/test/debug_timer.py pyrpl/test/durations.txt pyrpl/test/test_attribute.py pyrpl/test/test_base.py pyrpl/test/test_example.py pyrpl/test/test_hardware_modules/__init__.py pyrpl/test/test_hardware_modules/test_dsp_inputs.py pyrpl/test/test_hardware_modules/test_na_iir.py pyrpl/test/test_hardware_modules/test_pid_na_iq.py pyrpl/test/test_hardware_modules/test_sampler.py pyrpl/test/test_hardware_modules/test_scope.py pyrpl/test/test_hardware_modules/test_scope_asg_ams.py pyrpl/test/test_hardware_modules/test_trig.py pyrpl/test/test_load_save.py pyrpl/test/test_lockbox.py pyrpl/test/test_memory.py pyrpl/test/test_module_widgets.py pyrpl/test/test_na.py pyrpl/test/test_ownership.py pyrpl/test/test_proxyproperty.py pyrpl/test/test_pyqtgraph_benchmark.py pyrpl/test/test_redpitaya.py pyrpl/test/test_registers.py pyrpl/test/test_spectrum_analyzer.py pyrpl/test/test_validate_and_normalize.py pyrpl/test/test_widgets/__init__.py pyrpl/test/test_widgets/test_attribute_widgets.py pyrpl/test/test_widgets/test_module_widgets.py pyrpl/test/test_widgets/test_startup_widget.py pyrpl/test/test_widgets/test_yml_editor.py pyrpl/widgets/__init__.py pyrpl/widgets/attribute_widgets.py pyrpl/widgets/images/high_pass.bmp pyrpl/widgets/images/low_pass.bmp pyrpl/widgets/module_widgets/__init__.py pyrpl/widgets/module_widgets/acquisition_module_widget.py pyrpl/widgets/module_widgets/asg_widget.py pyrpl/widgets/module_widgets/base_module_widget.py pyrpl/widgets/module_widgets/curve_viewer_widget.py pyrpl/widgets/module_widgets/iir_widget.py pyrpl/widgets/module_widgets/iq_widget.py pyrpl/widgets/module_widgets/lockbox_widget.py pyrpl/widgets/module_widgets/module_manager_widget.py pyrpl/widgets/module_widgets/na_widget.py pyrpl/widgets/module_widgets/pid_widget.py pyrpl/widgets/module_widgets/pyrpl_config_widget.py pyrpl/widgets/module_widgets/schematics.py pyrpl/widgets/module_widgets/scope_widget.py pyrpl/widgets/module_widgets/spec_an_widget.py pyrpl/widgets/pyrpl_widget.py pyrpl/widgets/spinbox.py pyrpl/widgets/startup_widget.py pyrpl/widgets/yml_editor.py pyrpl3.yml pyrpl36.yml requirements.txt scripts/__init__.py scripts/fakerp_pyrpl.py scripts/run_pyrpl.py scripts/setup.py setup.cfg setup.py travis_global_config.yml <<<<<< network # path=/home/travis/build/lneuhaus/pyrpl/coverage.xml /home/travis/build/lneuhaus/pyrpl <<<<<< EOF